1. Field of the Invention
The present invention relates to a method for forming a gate electrode in a semiconductor device, and more particularly, to a method for forming a gate electrode having a narrow line width.
2. Description of the Related Art
Semiconductor memory devices may be categorized as random access memory (xe2x80x9cRAMxe2x80x9d) devices and read only memory (xe2x80x9cROMxe2x80x9d) devices. Generally, the RAM devices, such as dynamic random access memory (xe2x80x9cDRAMxe2x80x9d) devices and static random access memory (xe2x80x9cSRAMxe2x80x9d) devices, are volatile devices that lose data after a lapse of time. The data processing time for RAM devices, such as for input and/or output of data, is generally very fast. In contrast, ROM devices can generally maintain data indefinitely, but the data processing time for ROM devices is relatively slow. It is desirable for semiconductor memory devices to have a high degree of integration to form a great number of chips on a semiconductor substrate. Thus, the critical dimension (xe2x80x9cCDxe2x80x9d) of patterns accommodated in the memory devices becomes narrow. One or more transistor gate electrodes are typically included in each cell of a semiconductor memory device. Accordingly, the CD for the gate electrodes of these transistors becomes narrow.
The present invention addresses the above and other drawbacks and disadvantages of the prior art. Thus, first preferred embodiments of the present invention provide a method for forming a gate electrode of a semiconductor device that is capable of improving a characteristic variation of a cell by restraining the thickness of a gate oxide layer pattern from being increased when a re-oxidation process is carried out for forming the gate electrode.
Second preferred embodiments of the present invention provide a method for forming a cell gate electrode of a non-volatile memory device, capable of improving a characteristic variation of a cell by restraining the thickness of a gate oxide layer pattern and a dielectric interlayer pattern from being increased when a re-oxidation process is carried out for forming the cell gate electrode.
To achieve the first preferred embodiments of present invention, a preliminary gate electrode including a gate oxide layer pattern and a conductive layer pattern stacked on the gate oxide layer pattern is formed on a semiconductor substrate. A re-oxidation process is performed for forming the gate electrode by forming an oxide layer on an outer surface of the preliminary gate electrode and the semiconductor substrate, and supplying an oxygen gas and a chlorine-including gas into a reactor while restraining a thickness of the gate oxide layer pattern from being increased.
To achieve the second preferred embodiments of the present invention, a preliminary cell gate electrode is formed on a semiconductor substrate. The preliminary cell gate electrode includes a tunnel oxide layer pattern, a first conductive layer pattern stacked on the tunnel oxide layer pattern, a dielectric interlayer pattern stacked on the first conductive layer pattern, and a second conductive layer pattern stacked on the dielectric interlayer. A re-oxidation process is performed for forming an oxide layer on an outer surface of the preliminary cell gate electrode and on the semiconductor substrate by supplying an oxygen gas and a chlorine-including gas while restraining a thickness of the tunnel oxide layer pattern and the dielectric interlayer pattern from being increased.
According to another preferred embodiment of the present invention, a stacked structure of a tunnel oxide layer pattern, a first silicon layer pattern for a floating gate, and a nitride layer pattern are formed on a semiconductor substrate. A trench is formed by etching the semiconductor substrate using the stacked structure as an etching mask. A field oxide layer is formed for burying the trench. A dielectric interlayer and a second silicon layer for a control gate are sequentially formed on the first silicon layer pattern. A preliminary cell gate electrode having a stacked structure of the tunnel oxide layer pattern, the first silicon layer pattern, a floating gate pattern, an dielectric interlayer pattern, and the second silicon layer pattern, is formed by etching predetermined portions of the control gate and the dielectric interlayer. A re-oxidation process is performed for forming an oxide layer on an outer surface of the preliminary cell gate electrode and on the semiconductor substrate by supplying an oxygen gas and a chlorine-including gas onto the semiconductor substrate, including the cell gate electrode, while restraining a thickness of the tunnel oxide layer pattern and the dielectric interlayer pattern from being increased.
Since the oxygen gas and the chlorine-including gas are used for the re-oxidation process, the thickness of the gate oxide layer pattern can be restrained from being increased so that the thickness difference of the gate oxide layer pattern in each gate electrode can be reduced.